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k7p401823b - 1 - k7p403623b 128kx36 & 256kx18 sram rev 1.1 jul. 2003 document title 128kx36 & 256kx18 synchronous pipelined sram revision history rev. no. rev. 0.0 rev. 0.1 rev. 0.2 rev. 1.0 rev. 1.1 remark preliminary preliminary preliminary final final history - preliminary specification release - update dc characteristics x36 : i dd6 : tbd -> 300, i dd65 -> 290, i dd7 -> 280. x18 : i dd6 : tbd -> 290, i dd65 -> 280, i dd7 -> 270. - change simbol in dc characteristics i dd6 , i dd65 , i dd7 -> i dd65 , i dd70 , i dd75 - final version - add single ended differential clock on clock comment. draft date oct. 2002 jan. 2003 feb. 2003 jun. 2003 jun. 2003 the attached data sheets are prepared and approved by samsung elec tronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung el ectronics will evaluate and reply to your requests an d questions on the parameters of this device. if you have any ques- tions, please contact the samsung branch office near your office, call or cortact headquarters.
k7p401823b - 2 - k7p403623b 128kx36 & 256kx18 sram rev 1.1 jul. 2003 pin description pin name pin description pin name pin description k, k differential clocks(pecl or lvttl level) v ddq output power supply san synchronous address input m 1 , m 2 read protocol mode pins ( m 1 =v dd , m 2 =v ss ) dqn bi-directional data bus g asynchronous output enable sw synchronous global write enable ss synchronous select sw a synchronous byte a write enable tck jtag test clock sw b synchronous byte b write enable tms jtag test mode select sw c synchronous byte c write enable tdi jtag test data input sw d synchronous byte d write enable tdo jtag test data output zz asynchronous power down v ss gnd v dd core power supply nc no connection 128kx36 & 256kx18 sync hronous pipelined sram features functional block diagram ? 128kx36 or 256kx18 organizations. ? 3.3v v dd , 2.5/3.3v v ddq . ? lvttl 2.5/3.3v input and output levels. ? differential, pecl clock / single ended or differential lvttl clock inputs ? synchronous read and write operation ? registered input and latched output ? internal pipeline latches to support late write. ? byte write capability(four byte write selects, one for each 9 bits) ? synchronous or asynchronous output enable. ? power down mode via zz signal. ? jtag 1149.1 compatible test access port. ? 119(7x17) pin ball gr id array package(14mmx22mm). organiza- tion part number cycle time access time 128kx36 k7p403623b-h65 6 6.5 k7p403623b-h70 6.5 7.0 k7p403623b-h75 7 7.5 256kx18 k7p401823b-h65 6 6.5 k7p401823b-h70 6.5 7.0 k7p401823b-h75 7 7.5 sa[0:16] or sa[0:17] ck ss sw sw x g 128kx36 data in zz dqx[1:9] (x=a, b, c, d) or (x=a, b) (x=a, b, c, d) or (x=a, b) k k ck or 256kx18 array row decoder column decoder write/read circuit register 0 1 data out latch 1 read address register write address register latch sw register sw register latch sw x register sw x register ss register ss register 0
k7p401823b - 3 - k7p403623b 128kx36 & 256kx18 sram rev 1.1 jul. 2003 package pin configurations (top view) k7p403623b(128kx36) note : 1. nc* is used for the boundary scan. 2. nc** is reserved for trst input . 3. nc*** is reserved for hstl interface. 1 2 3 4 5 6 7 a v ddq sa 13 sa 10 nc sa 7 sa 4 v ddq b nc nc sa 9 nc sa 8 nc nc c nc sa 12 sa 11 v dd sa 6 sa 5 nc d dqc 8 dqc 9 v ss nc* v ss dqb 9 dqb 8 e dqc 6 dqc 7 v ss ss v ss dqb 7 dqb 6 f v ddq dqc 5 v ss g v ss dqb 5 v ddq g dqc 3 dqc 4 sw cnc*sw bdqb 4 dqb 3 h dqc 1 dqc 2 v ss nc* v ss dqb 2 dqb 1 j v ddq v dd nc*** v dd nc*** v dd v ddq k dqd 1 dqd 2 v ss kv ss dqa 2 dqa 1 l dqd 3 dqd 4 sw dk sw adqa 4 dqa 3 m v ddq dqd 5 v ss sw v ss dqa 5 v ddq n dqd 6 dqd 7 v ss sa 16 v ss dqa 7 dqa 6 p dqd 8 dqd 9 v ss sa 0 v ss dqa 9 dqa 8 r nc sa 15 m 1 v dd m 2 sa 2 nc t nc nc sa 14 sa 1 sa 3 nc zz u v ddq tms tdi tck tdo nc** v ddq km718fv4022(256kx18) note : 1. nc* is used for the boundary scan. 2. nc** is reserved for trst input . 3. nc*** is reserved for hstl interface. 1 2 3 4 5 6 7 a v ddq sa 13 sa 10 nc sa 7 sa 4 v ddq b nc nc sa 9 nc sa 8 nc nc c nc sa 12 sa 11 v dd sa 6 sa 5 nc d dqb 1 nc v ss nc* v ss dqa 9 nc e nc dqb 2 v ss ss v ss nc dqa 8 f v ddq nc v ss g v ss dqa 7 v ddq g nc dqb 3 sw b nc* nc nc dqa 6 h dqb 4 nc v ss nc* v ss dqa 5 nc j v ddq v dd nc*** v dd nc*** v dd v ddq k nc dqb 5 v ss kv ss nc dqa 4 l dqb 6 nc nc k sw adqa 3 nc m v ddq dqb 7 v ss sw v ss nc v ddq n dqb 8 nc v ss sa 16 v ss dqa 2 nc p nc dqb 9 v ss sa 1 v ss nc dqa 1 r nc sa 15 m 1 v dd m 2 sa 2 nc t nc sa 17 sa 14 nc sa 3 sa 0 zz u v ddq tms tdi tck tdo nc** v ddq
k7p401823b - 4 - k7p403623b 128kx36 & 256kx18 sram rev 1.1 jul. 2003 function description the k7p403623b andk7p401823b are 4,718,592 bit synchronous sram . it is organized as 131,072 words of 36 bits(or 262,144 words of 18 bits) and is implemented in samsung's advanced cmos technology. single differential pecl level k clocks or single ended or differen tial lvcmos/lvttl clock are us ed to initiate the read/write opera- tion and all internal operations are self-timed. at the rising edge of k clock, all addresses, write enables, synchronous selec t and data ins are registered internally. data outputs are updated from output latches of the falling edge of k clock. an internal wr ite data buffer allows write data to follow one cycle after addresses and c ontrols. the package is 119(7x17) ball grid array with balls on a 1.27mm pitch. read operation during reads, the address is registered duri ng the clock rising edge and the internal ar ray is read. the data is driven to the cpu in the following cycle. ss is driven low during this cy cle, signaling that the sram should drive out the data. during consecutive read cycles where the address is the same, t he data output must be held constantly without any glitches. thi s characteristic is because the sram will be read by devices that will operate slower than the sram frequency and will require mu lti- ple sram cycles to perform a single read operation. write(store) operation all addresses and sw are both sampled on the clock rising edge. sw is low on the rising clock. write data is sampled on the rising clock, one cycle after write address and sw have been sampled by the sram. ss will be driven low during the same cycle that the address, sw and sw[ a:d] are valid to signal that a valid operations is on the address and control input. pipelined write are supported. this is done by using write dat a buffers on the sram that capture the write addresses on one wri te cycle, and write the array on the next write cycle. the "next writ e cycle" can actually be many cycles away, broken by a serie s of read cycles. byte writes are supported. the byte write signals sw[ a:d] signal which 9-bit bytes will be writen. timing of sw[ a:d] is the same as the sw signal. bypass read operation since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a futur e read is to be done from the location that has not been written yet. for this case, the address comparator check to see if the new read add ress is the same as the contents of the stored write address latch. if the contents match, the read data must be supplied from the s tored write data latch with standard read timing. if there is no match, the read data comes from the sram array. the bypassing of the sram array occurs on a byte by byte bas is. if one byte is written and the other bytes are not, read data from the last written will have new byte data from the write data buffer and the other bytes from the sram array. low power dissipation mode during normal operation, asynchronous signal zz must be pulled low. low power mode is enabled by switching zz high. when the sram is in power down mode, the outputs will go to a hi-z stat e and the sram will draw standby current. sram data will be pre- served and a recovery time(t zzr ) is required before the sram resumes to normal operation. truth table k zz g ss sw sw a sw b sw c sw d dqa dqb dqc dqd operation xhxxxxxxxhi-zhi-zhi-zhi-zpower down m ode. no operation xlhxxxxxxhi-zhi-zhi-zhi-zoutput disabled. no operation llhxxxxxhi-zhi-zhi-zhi-zoutput disabled. no operation lllhxxxxd out d out d out d out read cycle l x l l h h h h hi-z hi-z hi-z hi-z no bytes written lxlllhhhd in hi-z hi-z hi-z write first byte lxll h l h hhi-zd in hi-z hi-z write second byte l x l l h h l h hi-z hi-z d in hi-z write third byte l x l l h h h l hi-z hi-z hi-z d in write fourth byte lxlllllld in d in d in d in write all byte
k7p401823b - 5 - k7p403623b 128kx36 & 256kx18 sram rev 1.1 jul. 2003 absolute maximum ratings note : stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a str ess rating only and functional operation of the device at these or any other co nditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol value unit core supply voltage relative to v ss v dd -0.3 to 4.6 v output supply voltage relative to v ss v ddq v dd v voltage on any i/o pin relative to v ss v term -0.3 to v dd +0.3 v maximum power dissipation p d 1.5 w output short-circuit current i out 25 ma operating temperature t opr 0 to 70 c storage temperature t stg -65 to 150 c recommended dc operating conditions note 1. for operation with differential pecl clock inputs. 2. for operation with single ended or differential lvcmos / lvttl clock input. parameter symbol min typ max unit note core power supply voltage v dd 3.15 3.3 3.45 v output power supply voltage (for 2.5v i/o) v ddq 2.375 2.5 2.9 v output power supply voltage (for 3.3v i/o) v ddq 3.135 3.3 3.6 v input high level (for 2.5v i/o) v ih 1.7 - v dd +0.3 v input low level (for 2.5v i/o) v il -0.3 - 0.7 v input high level (for 3.3v i/o) v ih 2.0 - v dd +0.3 v input low level (for 3.3v i/o) v il -0.3 - 0.8 v pecl clock input high level v ih -pecl 2.135 - 2.420 v 1 pecl clock input low level v il -pecl 1.490 - 1.825 v 1 clock input signal voltage v in -0.3 - 3.45 v 2 clock input differential voltage v dif -clk 0.2 - v dd +0.6 v 2 clock input common mode voltage v cm -clk 1.1 - 2.1 v 2 operating junction temperature t j 10 - 110 c
k7p401823b - 6 - k7p403623b 128kx36 & 256kx18 sram rev 1.1 jul. 2003 pin capacitance note : periodically sampled and not 100% tested.(dv=0v, f=1mhz) parameter symbol typ max unit input capacitance c in -5pf output capacitance c out -7pf dc characteristics note :1. minimum cycle. i out =0ma. 2. 50% read cycles. parameter symbol min max unit note average power supply operating current-x36 (v in =v ih or v il , zz & ss =v il ) i dd65 i dd70 i dd75 - 300 290 280 ma 1, 2 average power supply operating current-x18 (v in =v ih or v il , zz & ss =v il ) i dd65 i dd70 i dd75 - 290 280 270 ma 1, 2 power supply standby current (v in =v ih or v il , zz=v ih ) i sb -120ma1 input leakage current (v in =v ss or v ddq ) i li -1 1 a output leakage current (v out =v ss or v ddq , zz=v ih , g =v ih ) i lo -1 1 a output high voltage(i oh =-4ma) for v ddq =3.3v output high voltage(i oh =-4ma) for v ddq =2.5v v oh1 v oh2 2.4 2.0 v ddq v output low voltage(i ol =4ma) v ol v ss 0.4 v
k7p401823b - 7 - k7p403623b 128kx36 & 256kx18 sram rev 1.1 jul. 2003 ac characteristics parameter symbol -65 -70 -75 unit note min max min max min max clock cycle time t khkh 6.0 - 6.5 - 7.0 - ns clock high pulse width t khkl 2.0 - 2.0 - 2.0 - ns clock low pulse width t klkh 2.0 - 2.0 - 2.0 - ns clock high to output valid t khqv - 6.5 - 7.0 - 7.5 ns clock low to output valid t klqv - 2.5 - 2.5 - 3.0 ns clock low to output hold t klqx 0.5 - 0.5 - 0.5 - ns address setup time t avkh 0.5 - 0.5 - 0.5 - ns address hold time t khax 1.0 - 1.0 - 1.0 - ns write data setup time t dvkh 0.5 - 0.5 - 0.5 - ns write data hold time t khdx 1.0 - 1.0 - 1.0 - ns sw , sw [a:d] setup time t wvkh 0.5 - 0.5 - 0.5 - ns sw , sw [a:d] hold time t khwx 1.0 - 1.0 - 1.0 - ns ss setup time t svkh 0.5 - 0.5 - 0.5 - ns ss hold time t khsx 1.0 - 1.0 - 1.0 - ns clock high to output hi-z t khqz - 2.5 - 3.0 - 3.5 ns clock low to output low-z t klqx1 0.5 - 0.5 - 0.5 - ns g high to output high-z t ghqz - 2.5 - 3.0 - 3.5 ns g low to output low-z t glqx 0.5 - 0.5 - 0.5 - ns g low to output valid t glqv - 2.5 - 3.0 - 3.5 ns zz high to power down(sleep time) t zze -15-15-15ns zz low to recovery(wake-up time) t zzr -20-20-20ns z0=50 ? 50 ? 1.25v *capacitive load consists of all components ac test output load dout of the tester environment 20pf* ac test conditions parameter symbol value unit core power supply voltage v dd 3.15~3.45 v output power supply voltage v ddq 2.4~2.6 v input high/low level v ih /v il 1.7/0.7 v clock input high/low level(pecl) v ih/ v il 2.4/1.5 v input rise/fall time t r /t f 1.0/1.0 ns clock input rise/fall time(pecl) t r /t f 1.0/1.0 ns input and out timing reference level 1.25 v clock input timing reference level cross point v
k7p401823b - 8 - k7p403623b 128kx36 & 256kx18 sram rev 1.1 jul. 2003 timing waveforms of normal active cycles note 1. d3 is the input data written in memory location a3. 2. q4 is the output data read from the write data buffer(not from the cell array), as a result of address a4 being a match from the last write cycle address. 3. data is valid at the output at the later of t khqv following the rising clock edge, or t klqv following the fallowing clock edge. 4. when ss is sampled high or sw is sampled low on the rising edge of clock, the outputs go into hi-z state no later than t khqz following the rising clock edge. 5. when ss is low and sw is high on the rising edge of clock, the outputs go into low-z state(being driven) no earlier than t klqx1 following the next falling edge of clock. 6. when the sram is deselected, the output goes hi-z at t khqz following the rising clock edge. on the next read cycle, note that the sram output do not leave the hi-z state until t klqx1 after the falling clock edge. 12 34 5678 k san ss sw sw x dqn g a 1 a 2 a 3 a 4 a 5 a 4 a 6 a 7 q 1 q 2 d 3 d 4 q 5 q 4 t khkh t khax t avkh t khkl t klkh t khsx t svkh t wvkh t khwx t wvkh t khwx t klqv t khqz t wvkh t khwx t khqv t khqz t dvkh t khdx t ghqz t glqv t klqv a 1 t klqx t klqv t glqx t klqx1 t klqx1 9
k7p401823b - 9 - k7p403623b 128kx36 & 256kx18 sram rev 1.1 jul. 2003 timing waveforms of standby cycles 12345678 k san ss sw sw x dqn zz a 2 a 1 a 2 a 3 q 2 q 3 q 2 a 1 a 3 q 1 q 1 t khkh t zze t zzr t khqv t khqv
k7p401823b - 10 k7p403623b 128kx36 & 256kx18 sram rev 1.1 jul. 2003 jtag instruction coding note 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to vss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 4. sample instruction dose not places dqs in hi-z. ir2 ir1 ir0 instruction tdo output notes 0 0 0 sample-z boundary scan register 1 0 0 1 idcode identification register 2 0 1 0 sample-z boundary scan register 1 0 1 1 bypass bypass register 3 1 0 0 sample boundary scan register 4 1 0 1 bypass bypass register 3 1 1 0 bypass bypass register 3 1 1 1 bypass bypass register 3 ieee 1149.1 test access po rt and boundary scan-jtag this part contains an ieee standard 1149.1 compatible teat access port(tap). the package pads are monitored by the serial scan circuitry when in test mode. this is to support connectivity testing during manuf acturing and system diagnostics. internal data is not driven out of the sram under jtag control. in conformance with ieee 1149.1, the sram contains a tap controller, instruction reg - ister, bypass register and id register. the tap controller has a standard 16-state machine that resets internally upon power-up , therefore, trst signal is not required. it is possible to use th is device without utilizing the tap. to disable the tap control ler without interfacing with normal operation of the sram, tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the applicati on of a logic 1, and may be left unconnected. but they may als o be tied to v dd through a resistor. tdo should be left unconnected. jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo m 2 m 1 tdi tms tck tap controller state diagram test logic reset run test idle 0 11 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1
k7p401823b - 11 k7p403623b 128kx36 & 256kx18 sram rev 1.1 jul. 2003 boundary scan exit order(x36) 36 3b sa 9 sa 8 5b 35 37 2b nc nc 6b 34 38 3a sa 10 sa 7 5a 33 39 3c sa 11 sa 6 5c 32 40 2c sa 12 sa 5 6c 31 41 2a sa 13 sa 4 6a 30 42 2d dqc 9 dqb 9 6d 29 43 1d dqc 8 dqb 8 7d 28 44 2e dqc7 dqb 7 6e 27 45 1e dqc 6 dqb 6 7e 26 46 2f dqc 5 dqb 5 6f 25 47 2g dqc 4 dqb 4 6g 24 48 1g dqc 3 dqb 3 7g 23 49 2h dqc 2 dqb 2 6h 22 50 1h dqc 1 dqb 1 7h 21 51 3g sw c sw b5g 20 52 4d nc g 4f 19 53 4e ss k4k18 54 4g nc k 4l 17 55 4h nc sw a5l 16 56 4m sw dqa 1 7k 15 57 3l sw d dqa 2 6k 14 58 1k dqd 1 dqa 3 7l 13 59 2k dqd 2 dqa 4 6l 12 60 1l dqd 3 dqa 5 6m 11 61 2l dqd 4 dqa 6 7n 10 62 2m dqd 5 dqa 7 6n 9 63 1n dqd 6 dqa 8 7p 8 64 2n dqd 7 dqa 9 6p 7 65 1p dqd 8 zz 7t 6 66 2p dqd 9 sa 3 5t 5 67 3t sa 14 sa 2 6r 4 68 2r sa 15 sa 1 4t 3 69 4n sa 16 sa 0 4p 2 70 3r m 1 m 2 5r 1 boundary scan exit order(x18) 26 3b sa 9 sa 8 5b 25 27 2b nc nc 6b 24 28 3a sa 10 sa 7 5a 23 29 3c sa 11 sa 6 5c 22 30 2c sa 12 sa 5 6c 21 31 2a sa 13 sa 4 6a 20 dqa 9 6d 19 32 1d dqb 1 33 2e dqb 2 dqa 8 7e 18 dqa 7 6f 17 34 2g dqb 3 dqa 6 7g 16 dqa 5 6h 15 35 1h dqb 4 36 3g sw b 37 4d nc g 4f 14 38 4e ss k4k13 39 4g nc k 4l 12 40 4h nc sw a5l 11 41 4m sw dqa 4 7k 10 42 2k dqb 5 dqa 3 6l 9 43 1l dqb 6 44 2m dqb 7 dqa 2 6n 8 45 1n dqb 8 dqa 1 7p 7 zz 7t 6 46 2p dqb 9 sa 3 5t 5 47 3t sa 14 sa 2 6r 4 48 2r sa 15 49 4n sa 16 sa 1 4p 3 50 2t sa 17 sa 0 6t 2 51 3r m 1 m 2 5r 1 scan register definition part instruction register bypass register id register boundary scan 128kx36 3 bits 1 bits 32 bits 70 bits 256kx18 3 bits 1 bits 32 bits 51 bits id register definition part revision number (31:28) part configuration (27:18) vendor definition (17:12) samsung jedec code (11: 1) start bit(0) 128kx36 0000 00101 00100 xxxxxx 00001001110 1 256kx18 0000 00110 00011 xxxxxx 00001001110 1 note : 1. pins 6b and 2b are no connection pin to internal chip. these pins are place holders for 16m part and the scanned data are fixed to "0" for this 4m parts.
k7p401823b - 12 k7p403623b 128kx36 & 256kx18 sram rev 1.1 jul. 2003 jtag dc operating conditions note : 1. the input level of sram pin is to follow the sram dc specification. parameter symbol min typ max unit note power supply voltage v dd 3.15 3.3 3.45 v input high level v ih 1.7 - v dd +0.3 v input low level v il -0.3 - 0.8 v output high voltage(i oh =-2ma) v oh 2.1 - v dd v output low voltage(i ol =2ma) v ol v ss -0.2v jtag timing diagram jtag ac test conditions note : 1. see sram ac test output load. parameter symbol min unit note input high/low level v ih /v il 2.5/0.0 v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level 1.5 v 1 tck tms tdi tdo t chch t chcl t clch t dvch t chdx t clqv t mvch t chmx jtag ac characteristics parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5-ns tms input hold time t chmx 5-ns tdi input setup time t dvch 5-ns tdi input hold time t chdx 5-ns sram input setup time t svch 5-ns sram input hold time t chsx 5-ns clock low to output valid t clqv 010ns
k7p401823b - 13 k7p403623b 128kx36 & 256kx18 sram rev 1.1 jul. 2003 119 bga package dimensions 0.750 0.15 1.27 1.27 12.50 0.10 0.60 0.10 0.60 0.10 1.50ref c1.00 c0.70 14.00 0.10 22.00 0.10 20.50 0.10 note : 1. all dimensions are in millimeters. 2. solder ball to pcb offset : 0.10 max. 3. pcb to cavity offset : 0.10 max. indicator of ball(1a) location 119 bga package thermal characteristics note : 1. junction temperature can be calculated by : t j = t a + p d x theta_ja. parameter symbol thermal resistance unit note junction to ambient theta_ja tbd c/w junction to case theta_jc tbd c/w junction to solder ball theta_jb tbd c/w

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